The ADS8328 is a high-speed, low power, successive approximation register (SAR) analog-to-digital converter (ADC) that uses an external reference. The ADS8328 has an internal clock that is used to run the conversion but can also be programmed to run the conversion based on the external serial clock, SCLK.
The ADS8328 has two inputs. Both inputs share the same common pin—COM. The ADS8328 can be programmed to select a channel manually or can be programmed into the auto channel select mode to sweep between channel 0 and 1 automatically.
The ADS8327/28 can operate with an external reference with a range from 0.3 V to 4.2 V. A clean, low noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A 10-µF ceramic decoupling capacitor is required between the REF+ and REF– pins of the converter. These capacitors should be placed as close as possible to the pins of the device. REF– should be connected to its own via to the analog ground plane with the shortest possible distance. The test was performed on a breadboard with poor decoupling. The goal was to test the library and the SPI interface to be used in the final setup.
The ADS8327/28 has an oscillator that is used as an internal clock which controls the conversion rate. The frequency of this clock is 10.5 MHz minimum. The oscillator is always on unless the device is in the deep power-down state or the device is programmed for using SCLK as the conversion clock (CCLK).
Channel selection can be done both manual or automatically if auto channel select mode is enabled. The manual conversion mode is used and the conversion cycle starts with selecting an acquisition channel by writing a channel number to the command register (CMR).
The end of acquisition or sampling instance (EOS) is the same as the start of a conversion. This is initiated by bringing the CONVST pin low for a minimum of 40 ns. After the minimum requirement has been met, the CONVST pin can be brought high. A conversion can also be initiated without using CONVST if it is so programmed (CFR_D9 = 0). To have more control over the whole process the CONVST pin is used to start conversion.
The status pin is programmed as EOC and the polarity is set as active low, with this configuration the pin works in the following manner: The EOC output goes LOW immediately following CONVST going LOW when manual trigger is programmed. EOC stays LOW throughout the conversion process and returns to HIGH when the conversion has ended (as seen in the last picture).
The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for configuration data register (CFR).
Command Set Defined by Command Register (CMR)
The following table shows the Configuration Register (CFR) Map.
To start the communication first the CFR data is sent.
Then the converted values are read. The ADC reference is connected to 3,4 V and the channel is reading the 2,5 V from a DAC7564 internal voltage reference.